View 74LVQ74TTR_8696424.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/11 july 2001 n high speed: f max = 250 mhz (typ.) at v cc = 3.3v n compatible with ttl outputs n low power dissipation: i cc =2 m a (max.) at t a =25 c n low noise: v olp = 0.2 v (typ.) at v cc = 3.3v n 75 w transmission line driving capability n symmetrical output impedance: |i oh |=i ol = 12ma (min) at v cc = 3.0v n pci bus levels guaranteed at 24 ma n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 3.6v (1.2v data retention) n pin and function compatible with 74 series 74 n improved latch-up immunity description the 74lvq74 is a low voltage cmos dual d-type flip flop with preset and clear non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power and low noise 3.3v applications. a signal on the d input is transferred to the q output during the positive going transition of the clock pulse. clear and preset are independent of the clock and accomplished by a low setting on the appropriate input. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lvq74 dual d-type flip flop with preset and clear pin connection and iec logic symbols order codes package tube t & r sop 74lvq74m 74lvq74mtr tssop 74LVQ74TTR tssop sop
74lvq74 2/11 input and output equivalent circuit pin description truth table x : don't care logic diagram this logic diagram has not be used to estimate propagation delays pin no symbol name and function 1, 13 1clr, 2clr asynchronous reset - direct input 2, 12 1d, 2d data inputs 3, 11 1ck, 2ck clock input (low to high, edge triggered) 4, 10 1pr, 2pr asynchronous set - direct input 5, 9 1q, 2q true flip-flop outputs 6, 8 1q, 2q complement flip-flop outputs 7 gnd ground (0v) 14 v cc positive supply voltage inputs outputs function clr pr d ck q q l h x x l h clear h l x x h l preset l lxxhh hhl lh hhh hl hhx q n q n no change
74lvq74 3/11 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied recommended operating conditions 1) truth table guaranteed: 1.2v to 3.6v 2) v in from 0.8v to 2v dc specifications 1) maximum test duration 2ms, one output loaded at time 2) incident wave switching is guaranteed on transmission lines with impedances as low as 75 w symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 50 ma i cc or i gnd dc v cc or ground current 400 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2 to 3.6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time v cc = 3.0v (note 2) 0 to 10 ns/v symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 3.0 to 3.6 2.0 2.0 2.0 v v il low level input voltage 0.8 0.8 0.8 v v oh high level output voltage 3.0 i o =-50 m a 2.9 2.99 2.9 2.9 v i o =-12 ma 2.58 2.48 2.48 i o =-24 ma 2.2 2.2 v ol low level output voltage 3.0 i o =50 m a 0.002 0.1 0.1 0.1 v i o =12 ma 0 0.36 0.44 0.44 i o =24 ma 0.55 0.55 i i input leakage current 3.6 v i =v cc or gnd 0.1 1 1 m a i cc quiescent supply current 3.6 v i =v cc or gnd 22020 m a i old dynamic output current (note 1, 2) 3.6 v old = 0.8 v max 36 25 ma i ohd v ohd =2vmin -25 -25 ma
74lvq74 4/11 dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 3.3v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 3.3v. inputs under test switching: 3.3v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. ac electrical characteristics (c l = 50 pf, r l = 500 w , input t r =t f = 3ns) 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low (t oslh =|t plhm -t plhn |, t oshl =|t phlm -t phln |) 2) parameter guaranteed by design (*) voltage range is 3.3v 0.3v symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 3.3 c l =50pf 0.2 0.8 v v olv -0.8 -0.2 v ihd dynamic high voltage input (note 1, 3) 3.3 2 v v ild dynamic low voltage input (note 1, 3) 3.3 0.8 v symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t plh t phl propagation delay time ck to q 2.7 7.7 12.0 14.0 16.0 ns 3.3 (*) 6.3 9.0 10.5 12.0 t plh t phl propagation delay time pr or clr to q 2.7 6.9 12.0 14.0 16.0 ns 3.3 (*) 5.8 9.0 10.5 12.0 t w pulse width ck , high or low 2.7 4.0 1.5 4.0 5.0 ns 3.3 (*) 3.0 1.5 3.0 4.0 t w(l) pulse width pr or clr, low 2.7 4.0 1.5 4.0 5.0 ns 3.3 (*) 3.0 1.5 3.0 4.0 t s setup time d to ck high or low 2.7 4.0 -0.2 4.0 5.0 ns 3.3 (*) 3.0 -0.2 3.0 4.0 t h hold time d to ck high or low 2.7 2.0 0.2 2.0 2.0 ns 3.3 (*) 2.0 0.2 2.0 2.0 t rem recovery time pr or clr to q 2.7 1.0 -1.0 1.0 1.0 ns 3.3 (*) 1.0 -1.0 1.0 1.0 f max maximum clock frequency 2.7 100 200 100 80 mhz 3.3 (*) 120 250 120 100 t oslh t oshl output to output skew time (note1, 2) 2.7 0.2 1.0 1.0 1.0 ns 3.3 (*) 0.2 1.0 1.0 1.0
74lvq74 5/11 capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /n (per circuit) test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = 500 w or equivalent r t =z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 3.3 4 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz 33 pf
74lvq74 6/11 waveform1:propagation delays, setup and holdtimes (f=1mhz;50%dutycycle)
74lvq74 7/11 waveform 2:propagation delays (f=1mhz;50%duty cycle) waveform 3: recovery times (f=1mhz; 50% duty cycle)
74lvq74 8/11 waveform 4: pulse width
74lvq74 9/11 dim. mm. inch min. typ max. min. typ. max. a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 8.55 8.75 0.336 0.344 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.68 0.026 s8 (max.) so-14 mechanical data po13g
74lvq74 10/11 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 4.9 5 5.1 0.193 0.197 0.201 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop14 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0080337d
74lvq74 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - swit zerland - united kingdom ? http://w ww.st.com 11/11

▲Up To Search▲

Price & Availability of 74LVQ74TTR

	To Download 74LVQ74TTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .